The present invention relates generally to the field of automated design techniques for electronic circuits and, more particularly, to methods and systems for efficiently generating and checking physical layouts corresponding to libraries of electronic circuit cells.
Semiconductor manufacturing technology is constantly changing and advancing to realize smaller feature sizes in manufacturing, thus permitting the manufacture of faster, more dense and power efficient electronic circuits. Semiconductor chips, such as application specific integrated circuit chips (xe2x80x9cASICsxe2x80x9d) and custom logic chips, such as microprocessors and memories, are designed in this environment of change, often on short design schedules.
In order to utilize the latest changes and advances in semiconductor manufacturing technology for a particular chip design or designs, as well as to realize particular performance goals, such as low power and high-speed performance, the design process may often involve creating entirely new electronic circuits for every circuit on the chip or chips. This is challenging because modem chips are very complex, including millions of transistors and often a mile or more of wire interconnecting the transistors. In view of short design schedules and the complexity of chip designs, there is a substantial need for speed and accuracy during the chip design process and for systems to identify and correct design errors in newly designed electronic circuits prior to manufacturing.
One conventional way to improve the efficiency of the chip design process is through hierarchical design. Most, if not all chip designs include large numbers of groups of electronic circuits that perform an identical function. Therefore, it is convenient to identify these groups and design each group one time as a cell. The identical cells may then be instantiated many times on the chip during the design process to create the chip.
In hierarchical design, the lowest level of the design hierarchy is a cell conventionally called a xe2x80x9cleaf cell.xe2x80x9d The leaf cell is an electronic circuit implementing a particular function which includes only the fundamental circuit elements of the technology such as, for example, transistors, capacitors, inductors, resistors and diodes. Above the leaf cells in the design hierarchy are cells which may include other cells, leaf cells and/or fundamental circuit elements which are interconnected to realize a desired function. At the highest level of the design hierarchy, the entire chip is represented as interconnected cells in a single cell conventionally called a xe2x80x9croot cell.xe2x80x9d The root cell is analogous to the trunk of a tree, where each cell in the root cell is a branch off of the trunk of the tree. Each branch may include several levels of hierarchy between its interface with the trunk and the end of the branch, which is the leaf cell. The set of cells that are present in a chip design is generally referred to as a xe2x80x9clibraryxe2x80x9d and the set of leaf cells that are available for implementation in a chip design, are generally referred to as a xe2x80x9cmacro libraryxe2x80x9d or xe2x80x9ccell library.xe2x80x9d
The chip design process generally includes a logic design process and physical design process. In the logic design process, schematics representing the electronic circuits that comprise individual cells of the chip, as well as the entire chip, are created at each level of the design hierarchy to realize particular functional and performance goals. In the physical design process, the schematics of individual electronic circuits are transformed into the corresponding geometric shapes of mask works that are used in manufacturing the chip. The physical design process generally seeks to take advantage of the latest advances in semiconductor manufacturing technology by using minimum feature sizes to implement circuit elements where appropriate.
The logical and physical design processes are facilitated by the use of design automation tools. Typically, design automation tools run on a computer workstation, such as a UNIX based workstation. For example, during the logical design process, design automation tools called logic synthesis tools allow a chip designer to create schematics for cells at any or all levels of the design hierarchy. In addition, once a cell library representing the available leaf cells has been designed, design automation tools allow designers to automatically create or xe2x80x9csynthesizexe2x80x9d a schematic for an entire chip, or a substantial portion thereof, from a functional representation of a chip. The logic synthesis tools use the leaf cells of the cell library as building blocks for the chip design.
During the physical design process, design automation tools allow the automatic generation of the geometric shapes of the mask works directly from schematics on a cell-by-cell basis. The latter is typically done in stages. For example, in one stage, a cell schematic is conventionally converted into geometric shapes called xe2x80x9clayoutxe2x80x9d using a layout synthesis tool. The layout synthesis tool takes a cell schematic as input, and outputs a xe2x80x9csymbolic layoutxe2x80x9d for the cell by converting each circuit element, such as a transistor, capacitor, resistor or diode, into predefined geometric shapes or symbols representing a manufacturing plan for the circuit element. The layout synthesis tool also preserves connectivity between the circuit elements represented as symbols in the layout. In a later stage, the symbolic layout of the cell is compacted into a smaller area than it originally occupied, typically based on manufacturing groundrules defined for the desired semiconductor manufacturing technology. The compaction process is designed to increase the density of electronic circuits to the maximum extent permitted by the manufacturing technology.
During a chip design, the creation of the logical and physical designs of the leaf cells or xe2x80x9ccell libraryxe2x80x9d is critically important as the macro library forms the basic building blocks for the chip. Once the physical design of the leaf cells is completed, then the physical design of the chip may proceed by placing instances of the leaf cells and other cells into the root cell of the chip and routing wires between the leaf cells as defined by the hierarchy of the root cell schematic. In addition, data generated from the physical design of the leaf cells, such as input pin capacitance, drive strength and delay, are used in chip simulation to verify proper operation and performance and to make final logical design changes in view of the chip simulation.
There are several shortcomings to applying available design automation tools to the task of creating physical designs for a cell library. For example, conventionally, the process of creating layout for individual cells requires substantial manual intervention for each cell. In particular, manual intervention is required to make leaf cells conform to an overall plan for the macro library, such as uniform form factors and power buses and the inclusion of substrate and well contacts in cells. In addition, conventional tools for checking the integrity of the physical design, such as logical to physical and design rule checking tools, are not exhaustive. Thus, conventional processes leave the possibility for flaws in the physical design of the chip.
There is a need for an improved system for automated chip design that allows macro libraries to be generated quickly and directly from leaf cell schematics without substantial manual intervention. There is a further need to apply constraints to design automation tools to facilitate generation of a macro library which conforms to an overall plan. There is still a further need for additional checking of leaf cells to ensure correctness of the physical design of the leaf cell library and, therefore, manufacturability.
The above described problems and needs associated with automated chip design are addressed with a library tool suite according to embodiments of the present invention. The library tool suite supplements conventional design tools to increase the speed, automation and accuracy of creating physical designs for a library of cells to be used in chip designs. The tool suite may include a post operations tool, an audit tool, a custom interface, a setup file and a place and route model preparation utility which interact with the conventional tools and design data to automate and ensure integrity of the physical design process.
The tool suite facilitates automatically generating libraries corresponding to an overall cell plan, generating attributes defining a strength of connection between possible pin placements within a cell to facilitate routing inter-cell nets through the cell, and auditing cells for errors prior to inclusion in a manufacturing library.
According to one embodiment, a method creates layout for a cell library conforming to an overall plan. The method includes providing a set of design parameters corresponding to a cell. A symbolic layout of the cell is generated based on the design parameters. Constraints are specified on the cell according to an overall plan where the plan includes defining a cell boundary, power bus width and separation. The method further includes generating a compacted layout for the cell from the symbolic layout based on the constraints and generating substrate and well contacts to the compacted layout of the cell. Subsequently, the compacted layout, including the substrate and well contacts, is stored in a database.
In another embodiment of the present invention, the substrate and well contacts may be added based on a position of the cell boundary or based on a position of the power buses in each compacted layout. The constraints may further include at least one form factor constraint specifying a number of power buses per cell when a form factor of the compacted layout meets at least one predetermined condition.
In another embodiment of the present invention, the method may further include converting, identifying, designating and storing. In the converting step, each compacted layout is converted to a geometric layout where the geometric layout includes shapes defining input and output pins and wires connected to the pins. In the identifying step, for each compacted layout, the wires connected to the pins are identified. In the designating step, the wires connected to the pins are designated as weak connections and in the storing step the weak connection designations are stored in the database. The method may further include auditing at least one cell to identify any errors in the geometric layout.
An embodiment of a design automation system according to the present invention includes a memory, a design database and a processor. The memory includes program instructions comprising a compactor tool and a setup file. The setup file defines constraints on the compactor tool including constraints defining a cell boundary, power bus width and separation. The design database stores and retrieves electronic circuit design data and includes at least one symbolic layout corresponding to at least one leaf cell. The processor is coupled to the memory and the design database and executing the program instructions of the compactor tool to: read the setup file and the at least one symbolic layout, compact each of the at least one symbolic layout based on the constraints, and store a compacted layout for each symbolic layout in the database.
In another embodiment of the system, the memory may further include program instructions for a post operations tool. The processor may execute the program instructions for the post operations tool to: identify at least one shapes within the compacted layout, and automatically add substrate and well contacts to the compacted layout based on a position of the at least one identified shape. The at least one identified shape may includes a cell boundary or power buses.
In another embodiment of the present invention, the setup file further comprises at least one form factor constraint specifying a number of power buses per cell when a form factor of the compacted layout meets at least one predetermined condition.
In another embodiment of the invention, the memory further comprises program instructions for a utility and the processor executes the program instructions for the utility to: convert each compacted layout to a geometric layout where the geometric layout includes shapes defining input and output pins and wires connected to the pins, identify for each compacted layout the wires connected to the pins, designate the wires connected to the pins as weak connections, and store the weak connection designations in the database.
In another embodiment of the invention, the memory further comprises program instructions for an audit program and the processor executes the program instructions for the audit program to audit at least one cell to identify any errors in the geometric layout.
In another embodiment of the invention, a method of defining a cell to a routing tool comprises providing, determining, generating and storing. In the providing, a cell abstract is provided. The cell abstract includes design parameters describing the cell to a placement and wiring tool. The design parameters including net definitions. In the determining, at least two potential pin placements are determined along each of at least some of the nets. In the generating, an attribute for a pair of potential pin placements on the same net is generated. The attribute itself represents a strength of connection between the pair along the net. The storing includes storing the attribute for the pair in a database as associated with the cell.
A method of auditing a cell prior to including the cell in a library includes providing design parameters corresponding to a cell. Then determining: whether a cell boundary parameter of the cell is positioned correctly relative to an origin; whether more than one cell boundary exists; and determining a placement of other design parameters relative to the cell boundary. The method then indicates whether an error in the cell has been determined so that errors may be automatically identified and then corrected prior to inclusion in a library.